cenya's

ARM memory要inject fault比較簡單，且可以處理單個memory，比較符合我的需求
下 +define+ARM_FAULT_MODELING ＆ +define+ARM_NONREPAIRABLE_FAULT

並把ARM_NONREPAIRABLE_FAULT 這一段改成 memory 實際的hierarchy

最近也要對 Virage memory 做 fault injection
Solvent上有篇 "How can I inject fault into a specific memory instance in my design?" 可以參考(需要Solvent帳號)

裡面提到 There are four types of error injection mechanisms available to the user:

-- Memory standalone error injection
-- Virtual memory test-bench's fault injection
-- SMS component's standalone test-bench's fault injection
-- Top level error injection, hierarchically connecting to the specific memory

比較適合我的需求的是第一和第二種，但可惜此法不能個別 memory 埋 fault，要自己改一改
下 +define+MASIS_ERR_INJECT & +define+SUBCHIP_LEVEL & +error

這三個參數的描述如下

Snapshot from virtual memory's Verilog model:

 ` ifdef MASIS_ERR_INJECT
 //`define OUTPUT_DATA_DECLARED_REG
 `include "sadrlsih4m1p512x32m4b1w0c0p0d0t1s10_virt_modif_err_cntrl.inc"
 `endif

 Snapshot from virtual memory *_err_cntrl.inc file:

 `ifdef SUBCHIP_LEVEL
 if ($test$plusargs("error_fail")) unrep_err_inj;
 else if ($test$plusargs("error")) exact_err_inj(0,2);
 `endif

This mechanism is available for all types of virtual memories: repairable and non-repairable. The user should notice run-time plus-args, depending on the memory type: 

Example:  %: vcs *.v +define+MASIS_ERR_INJECT +define+SUBCHIP_LEVEL +error -l <logfile>.log
                 %: ./simv +error -l <logfilesim>.log

或是用 +define+MEMFAULTINJ & +asap_error

          Example:     %:  vcs *.v +define+MEMFAULTINJ -l< logfile>.log
                              %: ./simv +star_error -l <logfile_simv>.log

#####  後記  #####
因為實在需要每一顆memory都跑過fault injection來確認shared bus model的正確性
最後改test bench, 一顆一顆inject fault

initial begin
TB.CHIP.u_A.u_B.u_C.u_SRAM.fault_inject(10'd126,5'd6,1'd1);
end